1. Field of Invention
The present invention relates to memory I/O driver. More particularly, the present invention relates to a high-speed memory I/O driver with reduced noise.
2. Description of Related Art
Memory device has been widely used to store the information. The nonvolatile memory device can store information in a sufficient long period even when the power is off. When the multimedia industry has been well developed, memory card, which is a kind of portable memory device, has been widely used in current daily life to store information and transfer the information. Many newly developed digital apparatus, such as digital camera or computer, use the memory card to store multimedia information.
Usually, the digital device only adapts one memory card. However, when the amount of information greatly increases, the digital apparatus may adapt multiple I/O memory cards. When multiple memory cards are used, the driver needs to have high I/O speed to drive the memory cards. However, the I/O transient current is a big source of noise. The conventional driving circuit is shown in FIG. 1. The register 100 receives the data and the complimentary clock CLKB and then shifts the data to the output driver (OUTDRV) 102, which is controlled by an enable signal, OEB. The output of the driver 102 is exported to the I/O pad 104 with a voltage level with respect to the data. Then, the connected apparatus can read the data according to the voltage level on the pad 104. In addition, due to the circuit loop, there is an equivalent capacitor load (Cload) 106, exiting between the pad 104 and the system voltage Vss, such as a ground voltage.
FIG. 2 is a time diagram, schematically the relation between clock, data, and pad voltage, according to the conventional driving circuit in FIG. 1. Basically, the data as indicated by A is shifted out from the register 100, and is sent to the I/O pad 104 with amplification by the driver 102. Since the circuit has the loading capacitor 106 and the equivalent impedance, the waveform of data signal on I/O pad has slopes on the rising edge and/or the falling edge. Also, the time response is not precisely following the signal A. As a result, when the data signal on the I/O pad is read out at the falling edge of the clock CLK, due to the data setup time from PAD to the next rising edge of the clock CLK, a strong driving capability is needed, power and Vss bounce may induce the noises and the data would be erroneous. This error is more often when multiple memory cards or multiple I/O pads in a memory card are adapted together.
When at least considering above conventional issues or some other potential issues, the conventional memory-card driver is necessary to be further developed.